Whale Inspired Optimization Algorithm for Optimal Design of Low Voltage Amplifier

This paper discusses the application of a new nature-inspired optimization algorithm, called Whale Optimization Algorithm (WOA), to the resolution and optimization of singleand multi-objective problems in microelectronic design field. The performances of WOA are tested on one of the more interesting analog integrated circuits (ICs), for low supply voltage applications, the low-voltage amplifier (LVA). After identifying and determining the constraints of the LVA circuit, WOA is used to optimize MOS transistors sizes. This allows the best gain, the largest bandwidth and the highest slew rate. These main characteristics are optimized in two ways. In the first step, each function is optimized on its own, keeping the others fixed. In the second, the three characteristics are combined, with equal weights, to form a single main objective function. WOA is coded in MATLAB and the obtained results are confirmed by Cadence Virtuoso simulations in CMOS 0.18μm technology. The simulation results are 88.8dB (88.73dB), 23.92V/μs (20.52V/μs) and 24.6MHz (25.5MHz) for DC gain, slew rate and gain bandwidth in the single (multi)-objective experiment, respectively, justifying that WOA is an effective method for the design of the above mentioned circuit.


Introduction
In the past years, the significant growth of consumer electronics devices triggered a major increase in micro-and nano-electronics activities, allowing the IC market to grow from almost $10 billion in 1980 to more than $400 billion in 2020 (World Semiconductor Trade Statistics) [1]. Due to the continuous progress in VLSI technologies, engineers are able to integrate in a single chip, the whole necessary electronic compounds for a System On Chip (SOC). Generally, integrated electronic circuits are composed of digital and analog parts. Analog circuits form the dominant block of electronic systems serving as an interface between digital parts and real signals [2]. These circuits are formed of hundreds of transistors and their importance cannot be neglected as their size imposes major constraints on their design, overall cost and performance [3]. If the digital IC design is an automatic task, the analog IC design remains a time-consuming, iterative and complex process. Achieving analog circuit design within strict time to market constraints is a real challenge. This is because of the demand for devices with lower production costs, better efficiency and integration costs, and lower design costs. New analog IC optimization and design methods should then be introduced to ensure optimal performance of the solutions regarding the design specifications. For simple specifications, circuits with one to two functions and few parameters, can be designed using the knowledge of designers [4]. However, for more complex circuits with a large number of transistors and many functions and constraints, one of the most challenging tasks for designers is to choose the optimal design respecting the constraints. The accomplishment of this difficult task is possible because designers are supported by computer-aided design tools assisting in the overall design process. Therefore, efficient simulation-based optimization techniques [5][6][7][8][9][10][11] or models-based techniques [12][13][14][15][16][17][18] are important for the optimal design of highperformance analog circuits. Metaheuristic optimization algorithms are recommended in such a case to generate good solutions in a reasonable time because they: 1) rely on quite simple concepts and are easy to implement; 2) can bypass local optima; 3) can be used for a wide range of problems in different disciplines [19]. Several metaheuristics have been suggested for the optimization of analog circuits, namely, particle swarm optimization (PSO) [20], butterfly optimization algorithm (BOA) [12], ant colony optimization (ACO) [21], genetic algorithm (GA) [22], simulated annealing (SA) [23], grey wolf optimization (GWO) [24], etc., These algorithms have proved to be useful and interesting in this field and their variety clearly shows that the debate remains open and that new methods are welcome to enrich this field of investigation. In this paper, we present an adaptation of the WOA algorithm for the analog integrated circuit design. The two-stage amplifier for low supply voltage applications is used as a complex circuit for testing the performance of the proposed optimization algorithm. The conception is performed in the CMOS 0.18µm technology parameters. The optimization results obtained by the WOA were evaluated and confirmed by the Cadence Virtuoso tool in the framework of the same technology. Simulation results show that the WOA algorithm works well and reaches its optimal results, corresponding to the required specifications for the circuit, much faster than other methods with even improved characteristics.
This paper is organized as follows: In section 2 the proposed algorithm details and its evaluation are presented. Section 3 presents the optimization of the analog circuit and the simulation results using Cadence Virtuoso. Section 4 shows simulation results and discussion. Finally, section 5 concludes the paper.

Whale Optimization Algorithm
The whale optimization algorithm is one of the recent nature-inspired meta-heuristic algorithms. Proposed by Mirjalili et al. in 2016 [19], WOA is a population-based approach. It is inspired by the special hunting technique of humpback whales. This technique is called the bubble-net feeding. In this feeding method, humpback whales swim around the prey and form a distinctive air bubbles around a circle or 9-shaped path. For more details about the bubble net feeding and hunting methods, see reference [19].

Encircling prey
Humpback whales are able to recognize the position of prey and encircle them. As the optimal design position in the search space is not known a priori, the WOA approach assumes that the target prey is the best current solution. Then, all other search agents try to improve their positions in relation to the best search agent. This procedure is expressed by [19] : (4) C and A are coefficient vectors, ⃗ X and ⃗ X * are respectively the actual and the best position vector obtained so far. ⃗ X * is updated at each iteration t if a new better solution is found. r is a random vector in [0,1] and a is linearly decreased from 2 to 0 over the iterations.

Bubble-net feeding method
The bubble-net feeding of humpback whales (exploitation phase) can be modeled by two approaches:

Shrinking encircling prey This behavior can be obtained by decreasing a in Eq. 3. This means that
Using random values for A in [−1, 1], the new position can be set anywhere between the original agent and the current best agent positions. Figure 1a shows the possible positions from (X, Y ) to (X * , Y * ) which can be achieved by 0 ≤ A ≤ 1 in a 2D space.

Spiral updating position
As can be seen in Figure 1b, this method first calculates the distance ⃗ D ′ between the located whale at (X,Y) and located prey at (X * , Y * ). A mathematical spiral equation to update the position of humpback whale to prey is created to mimic the helix-shaped movement of whales is given by: Where ⃗ D ′ is the distance between the i th whale to the prey, b is constant equal to 1 and l is random number in [−1, 1]. Humpback whales all swim simultaneously around the prey within a shrinking circle and along spiral path. To model this behavior, we assume that there is a 50% probability (p) of choosing between the spiral model or the shrinking circling mechanism to update the position of the whales during optimization. Considering p as a random probability in the interval [0, 1], we consider the smallest probability for the shrinking swim and the highest for the spiral trajectory as indicated by Eq. (7):

Search for prey
The same method based on the variation of A can be used to search for prey. Indeed, humpback whales randomly search depending on the position of others. Therefore, to force the search agent to move far away from a reference whale, we use A with random values less than -1 or greater than 1. Unlike the exploitation phase, the position of a search agent in this phase is updated by a randomly selected search agent instead of the best search agent found so far. This mechanism with | A |> 1 allow the WOA algorithm to perform a global search. The mathematical model is given by : Where ⃗ X rand is randomly chosen from the current population of whales. The WOA approach begins with a population of random solutions, then at each iteration, the search agents update their positions either on the best solution obtained to date, or on a research agent selected at random. The parameter a is linearly decreased from 2 to 0 over iterations to ensure exploration and exploitation, respectively. When | A |< 1, the best solution is chosen, while a random search agent is selected when | A |> 1 to update the position of search agents. Finally, WOA stops when the stop criteria are met. The proposed algorithm is given in Figure 2.

Evaluation of the used algorithms
The robustness of the proposed and used, for comparison algorithms, is tested by using mathematical classical test functions. Table 1 present the used functions, the variable limits and theoretical results and experimental minimums achieved by the algorithms for a population of 100 and 1000 iterations. The experimental results show that all algorithms achieve good results, we can also notice that WOA achieves a global minimum of each function and can be successfully used for optimization problems.

Functions
Ranges [−5.12, 5.12] 0 0.00E-00 0.00E-00 0.00E-00 3. Application of the WOA for the optimal design of the LV Amplifier Figure 3 shows the schematic diagram of the low-voltage two stage CMOS operational amplifier under study. It is formed from a simple n-channel differential input stage with current source loads (M3-M4), allowing the largest possible Input Common Mode Range (ICMR) without cascode or parallel input stages. M6 and M7 are biased so that the voltage across the sources and drains of the M3 and M4 corresponds to the saturation voltage V SD (sat).

The low voltage two stage amplifier
The output current signals of the differential stage are folded across M6 and M7 transistors and converted to the output stage with M8 and M9. C C and C L are respectively the compensation capacity and the load capacity. The main advantages of this amplifier topology in comparison to the traditional two-stage amplifiers are: high gain, lower supply voltage, balanced input differential stage loads [25]. The targeted optimal characteristics are: the DC gain, the bandwidth and the slew rate:

Voltage gain
The open loop voltage gain is the product of the first and second stage gains : where g mi , g dsi are respectively the gate trans-conductance and the output conductance of i th transistor.

Slew Rate
The slew rate SR is given by: where I 5 is the drain current of the transistor M5.

Gain Bandwidth
The gain bandwidth GBW is given by:

Input common mode range
• Positive ICMR V Imax The maximum input voltage is given by the sum of the voltages from the amplifier input to V DD when the input is at V in (max).
where I 3 is the drain current of transistor M3. µ 0 and C ox denote respectively the electron mobility and the oxide capacitance. V th1 is the threshold voltage of M1. W i and L i denote the gate width and the channel length of the i th transistor.
• Negative ICMR V Imin The minimum input voltage occurs when the amplifier input is pulled to V SS and M1 and M2 just enter the linear mode.
3.1.5. Output swing The output swing is obtained from the minimum and maximum output voltages that allowing all transistors to run in the saturation mode.
• Maximum output voltage : • Minimum output voltage : The amplifier circuit is designed in CMOS 0.18µm technology using Cadence Virtuoso. The design parameters for this amplifier are the transistors channel lengths (L) and widths W, the compensation capacitor C C and the bias current I bias . During design, the supply voltages V DD(SS) and the load capacity C L are kept at ±1.5V and 10pF, respectively. The good operation of the amplifier is ensured by the matching relations of the transistors, M1≡M2, M3≡M4≡M15, M7≡M6, M8≡M9, M5≡M10, M11≡M12 and to reduce the channel modulation effect, the channel lengths are set to three time the minimum value. Table 2 shows the design parameters and their fixed ranges. For simplicity, a small interval for M1 is considered because the current of transistor M5 is twice the current of M1. We also considered a large interval for M13 because the current flowing through it is higher.
We proceed in two different steps, in the first one we optimize only one characteristic keeping fixed the others whereas in the the second step, we gathered the three parameters in a single objective function, giving them the same weight. In all experiments, the other performances are used in constraints to avoid their degradation. C c (pF) 3 3 x 10 I bias (µA) 45 120

Problem Formulation
To be successfully designed, amplifiers should be designed according to the specifications required by the application and should meet the design constraints. In all experiments, the WOA is employed to design the circuit taking into account the following constraints, Phase Margin (PM) ≥ 60 • , V Imin ≤ 0.8V, V Imax ≥ 1.8V, V Omin ≤ 0.4V and V Omax ≥ 1.3V. In addition, the design specifications for the chosen experiments are given in Table 3. Table 3. The set of specifications for the LV amplifier Step 1 Step 2 experiment 1 experiment 2 experiment 3 Spec. Target Spec. Target Spec. Target Spec. Target In the second step, the amplifier design is optimized by transforming the optimization problem to a singleobjective one by a linear association of the three important functions. We assigned the same weight to the chosen objectives as they are all important for the amplifier design.
The normalized function is given by: Where α = β = γ = 1/3, correspond to the weightings parameter for the DC gain, slew rate and gain bandwidth, respectively. These weights can be changed by designers according to each requirement. A vmax , SR max and GBW max are the maximum values of the A v , the SR and the GBW, respectively.

Simulation results and discussion
The amplifier was first optimized using the WOA and by PSO and ACO algorithms for comparison purposes. The algorithms were executed on a computer with an Intel Core i7-7820HQ 10@2.90 GHz (8 CPUs) and 16G memory. Tables 4, 5 and 6 show, respectively, the optimization results and the convergence times for A v , SR and GBW. These tables also report the simulation results performed by Cadence Virtuoso.  From these tables it can be seen that the proposed algorithm provides the best results compared to the other methods in all experiments. It is evident from the results that all requested specifications are fully satisfied, and reasonably match with the simulation results from CADENCE Virtuoso. It can be also noted that WOA takes a minimum convergence time to attain its global optima.
The results of the multi-objective optimization are presented in table 7. This table also shows the convergence time and the simulation results. We can see that the best trade-offs between the objectives i.e, A v , SR and GBW, are achieved by the WOA approach in a minimal convergence time. One can also see that the obtained results are in good agreement with the simulations showing that the WOA has a powerful efficiency in analog circuit sizing problems.
The AC response and the transient simulation of the LV amplifier, as obtained from circuit simulations for typical conditions are shown in Figures. 4 and 5, respectively. The values of the DC gain, the bandwidth gain, the phase margin and the slew rate obtained from the proposed design match reasonably well with those obtained from circuit simulations. This substantiates the validity of the proposed method for the LV amplifier design.

Process, voltage and temperature (PVT) variations
To show the robustness of the LV amplifier design, the PVT corners including supply voltage variations (0.9V DD , V DD , 1.1V DD ) and temperature changes (-55 • C, 27 • C , 100 • C) are simulated with Cadence for the second step of optimization experiment. Figure 6 shows the AC simulation results of the PVT analysis. In this figure, the blue curve refers to typical simulation (+27 • C, V DD ) while the red curves show the simulation results, by varying the temperature and the supply voltages. For typical corners, the open loop gain and the bandwidth are 88.73dB and 25.5MHz and show a maximum variation of 2dB and 3.01MHz which means that the designed circuit has a robust behaviour and is stable against PVT analysis.
The transient simulations to input step of ±1V are shown in Figure 7 where V out is the output voltage of the amplifier in a negative feedback as a voltage follower. The same temperature and voltage variations are used. For typical corners, the slew rate is 20.5V/µs and shows a maximum variation of 1.5V/µs.

Conclusion
In this paper, a new optimization method for analog circuit design is successfully introduced. It is inspired by the whale strategy for food searching. The test circuit is the two-stage low voltage amplifier. For comparison purposes, the ACO and PSO algorithms are used for the same problem resolution. Before their application, some robustness tests have been carried out to verify the correct convergence of these used algorithms. Through many experiments, we have shown that this algorithm allows to achieve rapidly better results despite the great complexity of the optimized circuit. The achieved results show that the proposed algorithm beside providing efficient results, can be useful for the optimization of analog circuits. The optimization results are in good agreement with obtained simulations with the Cadence Virtuoso in CMOS 0.18µm technology.